|
The
68000 CPU-2.1 Board |
|
This
is an updated 68000 CPU-2 Board.
The board
provides the same features as the earlier board i.e.
|
| |
| Space saving
PLCC 68000 CPU |
| POR (Power On
Reset) and
manual reset circuitry |
| The CPU/System
clock oscillator module |
| CPU Halt &
Reset state indicators |
| Binary display
of the upper 2 address lines (A23 & A22) |
| Self Test -
alone this board can be configured to 'free run'. The
68000 cycles through
its entire address range performing an op-code fetch at each
address. |
| Bus Error
support |
| Full interrupt
support including NMI with optional push button NMI. |
| |
| NEW
Feature: |
| Jumper
selectable biasing of the 68000 data bus - the bus can now be biased high or low. |
 |
| |
| |
| |
| |
| |
| |
| |