|
Quartus II |
| Quartus II Web
Edition is a FREE software
download used here to program the following parts: |
| |
| EPM7032SLC44 |
| EPM7064SLC44 |
| EPM7128SLC84 |
| |
| These parts
are electrically erasable complex programmable logic devices
(CPLD's). |
| |
| To program
these parts you will need
the following: |
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| Software |
| |
| Quartus II
64-Bit Version 13.0.1 Build 232 06/12/2013 SJ Web
Edition + Service Pack 1 |
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| Hardware |
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| USB Blaster
Programmer |
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| Altera
MAX 7000S series CPLD's |
| |
|
Mega-68000
Computer System boards to-date have typically used one
or more Generic Array Logic devices (GAL's) to
significantly reduce the chip count. This space saving
solution has worked well, however Quartus II allows
substantially more logic elements to be placed on a
single Altera MAX 7000S series CPLD device and so offers
a single chip glue logic solution for some new board
designs requiring an even higher level of integration. |
| |
| Quartus II
- starting a
new project |
| |
|
1. |
Launch
the Quartus II Software |
|
2. |
Select
'create a new project (new project wizard)' |
|
|
'Directory, Name, Top-Level Entity [page 1 of 5]'
of the new project wizard appears |
|
3. |
Specify the working directory for the project
and the name of the project |
|
|
|
e.g. |
|
d:/my projects/68000/cpld code/cpld1
|
|
cpu_logic |
|
|
4. |
Click
the 'Next' button |
|
|
'Add Files
[page 2 of 5]' of the new project wizard appears |
|
5. |
Click
the 'Next' button (i.e. skip this page) |
|
|
'Family &
Device Settings [page 3 of 5]' of the new project
wizard appears |
|
6. |
Specify the device family and target device |
|
|
|
e.g. |
|
MAX7000S |
|
EPM7128SLC84-15 |
|
|
7. |
Click
the 'Next' button |
|
|
'EDA Tool
Settings [page 4 of 5]' of the new project wizard
appears |
|
8. |
Click
the 'Next' button (i.e. skip this page) |
|
|
'Summary
[page 5 of 5]' of the new project wizard appears |
|
9. |
Click
the 'Finish' button |
|
| |
| Quartus II
- adding a Block Diagram / Schematic File |
| |
|
1. |
Click
'New' on the File menu |
|
2. |
Select
'Block Diagram/Schematic File' |
|
3. |
Click
the 'OK' button |
|
4. |
Click
'Save All' on the File menu |
|
| |
|
It is now possible
to construct the logic internal to the CPLD using the
Block Diagram / Schematic File Editor. Standard logic
elements (gates, flip-flops, etc.) can be added and
then connected together using the applications wire tool, no
understanding of a complex programming language is
required. |
| |
| Quartus II
- using the Editor |
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| Keyboard
commands: |
| |
|
ESC |
Cancel |
|
CTRL+SPACE |
Zoom
In |
|
CTRL+SHIFT+SPACE |
Zoom
Out |
|
| |
| Useful logic
elements: |
| |
|
AND2 |
2
Input AND Gate |
|
OR2 |
2
Input OR Gate |
|
NAND2 |
2
Input NAND Gate |
|
NOR2 |
2
Input NOR Gate |
|
NOT |
Inverter |
|
TRI |
Tristate Buffer |
|
INPUT |
Input Pin |
|
OUTPUT |
Output
Pin |
|
VCC |
Pull
Up |
|
GND |
Pull
Down |
|
| |
| Double clicking
an input/output pin allows the default pin label to be changed
to something more meaningful. |
| |
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