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68000 68030 CPLD FPGA ARM
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The Memory-2 Board
J1 BVD - Boot Vector Disable
 
Placing a Jumper (as shown in RED below) disables Mode 0 or BV (Boot Vector) Mode.
 
Mode 0 or BV (Boot Vector) Mode   Mode 0 or BV (Boot Vector) Mode
DISABLED   ENABLED
 
JB1 P39 - ROM Configuration
 
This Jumper Block allocates either the upper 256K or the lower 256K of the 512K ROM to the ROM address space (FC0000h - FFFFFFh).

Alternatively the whole 512K of ROM can be allocated to the address range F80000h - FFFFFFh.

Note:

For the 512K ROM option to work correctly IC2 pin 6 needs to be isolated and tied high, or (better) IC2 reprogrammed so that A18 plays no part in IC2's ROM address decoding scheme.

The desired option can be set with a Jumper (as shown in RED below).

   
Lower 256K   Upper 256K   512K
00000h - 3FFFFh   40000h - 7FFFFh   00000h - 7FFFFh
00000h - 1FFFFh (16)   20000h - 3FFFFh (16)   00000h - 3FFFFh (16)
 
Memory-2 Board - Jumpers highlighted in RED
 
 
 
 
 
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